#1
  • fixed low level usb handling (hotplug is reliable now)
  • fixed cycles position ii message range

please post ansible bugs here in this thread. i know there are possibly some i2c issues lurking still, so please post your experiences with as much detail as possible.

10 Likes
Telex: Teletype expanders
#2

awesome! thanks for your work on this - can’t wait to test it out this evening.

i was wondering - has that stepped cycles bug been solved? i just noticed it happening on mine last night. haven’t updated for a while though…

#3

yes, that was a dac init issue. fixed.

#4

wonderful! thanks again :slight_smile:

#5

@tehn

I installed the new firmware and while playing around with kria and a simple script on teletype with just clocking kria from M TR.PULSE 1 and resetting it with 1 KR.RES 0 0, KR.RES 1 0 I lost Grid control. It still showed what was happening but I button presses had no effect. Kria itself did run and stopped when the clock signal stopped.

After power cycling I wrote this test script on teletype:

I

TR.TIME 1 10
M 50

M

TR.PULSE 1

1

KR.RES 0 0
KR.RES 1 0

It froze again and after power cycling teletype stays black…

I am pretty sure about the script and that I programmed it into an empty preset. The only mistake I might have made is a typo in M, writing TR.TIME 10.

I reflashed teletype to get it working again and tried again but found that KR.RES acts weird. It seems to reset the pitch parameter to the last step instead of the first one and creates strange patterns on the grid:

#6

how many modules on the i2c bus?

does teletype unfreeze if you simply start up the ansible with kria running?

#7

Two Ansibles, MP and ES on the i2c bus.

Teletype did not start with Kria running on Ansible.

After reflashing tt I could not reproduce it by now.

Regarding the messed up grid from the video I found that it has nothign to do with KR.RES but alway gets messed up when you use the two finger press on the grid that sets loop start and length of a pitch pattern setting it up in a way that the start comes after the end (hell, I cannot explain this in english - setting a loop from 8 to 3 for example and let it wrap around on the right edge of the grid).

EDIT: TR.TIME 10 freezes tt, which seems to be logical since there is no TR 10 output…so it might have been a typo and the known freeze on unknown destination bug.

#8

here’s a tt version with pullups enabled, hoping to clean up the i2c bus traffic

#9

I cannot get Levels to a full pattern with LV.L.LEN 16

LV.L.LEN 15 does work though but leaves one position empty. All other lengths are possible too.

#10

please try this one:

#11

This version does not work either in this aspect. While LV.L.LEN reads out the length properly from 1 to 16 it is not possible to set LV.L.LEN 16. It simply ignores the command and Length stays on the value it has been before.

#12

i’m not looking into this bug you’ve reported yet-- so i don’t promise anything different unless it’s related to i2c issues, which is what i’m trying to work on right now.

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#13

Ah okay - then I somehow misinterpreted your post above.

i2c is clearly more important atm.

:slight_smile:

#14

i can do a fix for LV.L.LEN tonight, looks like an easy fix.

2 Likes
#15

the fix for LV.L.LEN is done, but hasn’t been incorporated into the master branch yet. if you’d like to try it in the meantime here is the hex file:

ansible.hex (219.2 KB)

1 Like
#16

Yes, this workes - thank you for the fix!

1 Like