@24Franks suggested we post this in the forum to 1) get some feedback and 2) check for overlap with other projects that could speed this up. tldr warning.
Our intention is to have a grids control a switch matrix (any signal: audio, cv, gate, trig, etc) that could be daisy chained 8x8 i/o modules controlled via i2c. (Ansible? Teletype? or Other?)
Why 8 x 8? (and not 8 x 16)
It seems more beneficial to use half the space on the grids for ui (saved routings, paging between different 8 x 8 blocks, sequencing?, etc…)
with the trend of sending i2c via differential signal it appears this can travel over some distance now without too much interference. even the cheapest mcus have i2c support.
we are aware of the SSSR 8x16 which seems like a relatively easy integration (read on another forum this was intended from the outset) but the i/o is not buffered and to my knowledge while it is fairly comprehensive (12vpp) it is not totally “safe” for more, shall we say, impromptu, patching (a voltage outside the range could damage the switch ic).
option 1 (arm based)
we originally thought just run everything through an mcu running at audio rate and while this is definitely being experimented with it poses certain drawbacks:
1. likely an ARM based MCU with 32 bit FPU support which aren’t really widely available at the moment… (unless you know of a place?)
2. inclusion of 2 relatively expensive (and also possibly hard to find) DAC/ADC ICs
The benefit as we see it to using this approach you could use some fast compression algorithms and handle the problem of summing voltages. To me this seems really comprehensive and interesting but is this necessary though? perhaps someone with more EE knowledge could fill in…
option 2 crosspoint ic + atmega168/368
there is an 8x8 version of the ic in the SSSR switch matrix. one could potentially just add buffered i/o to safely scale input and output to always within the range the ic can accept. the ic can be controlled via a cheap atmega (like the sssr) which can also receive instructions via i2c.
the drawbacks here are that, to my knowledge, if at any moment two signals summed adds up to > +/-12 its possibly not good for gear… (am I conceiving this correctly? or is this a non-issue?)
the obvious perks here are the price and availability of the ics. ~ $25 for the ics ( < $10 if you ditch the buffers and basically just make an 8 x 8 ssri clone with the grids as the interface )
- are there any current undertakings happening here?
- is there someone with more of an ee background that could clear up the necessity/triviality of “compression” on the summed signals for euro?
- for those that think this would be cool… is it worth being a bit more careful (pre-scaling voltages using other modules) for the benefit of it being cheaper and done sooner?
we’ve started some minor prototyping and should have some demo pcbs done soon for both versions. in lieu of having an ansible/teletype at the moment we’ll probably be using a teensy 4.1 to connect the grids to euroland/i2c (pcb also available soon)