i was also curious about this, so i took a look at the mechanisms:
all the triggers are on port 0, line 0, so they all share an IRQ: (IRQ source)
i think, but i’m not 100% sure, that if the trigger is truly simultaneous - meaning same wire / ports change value within one clock cycle - then the IRQ will be entered once, with the relevant flags set in the GPIO status register.
therefore, that looping structure alone determines the order in which simultaneous trigger events are pushed to the event queue.
unfortunately, this behavior is dependent on magic numbers. the index of the trigger is assumed to be the physical pin number (index is passed directly to this function.) i guess this is fine as long as nothing ever changes! but it’s fragile and not obvious.
i would always prefer to explicitly test pins based on their function, not on their physical layout, with all functions defined in the board conf header:
i know it looks “non-minimalist” but this is more maintainable. you don’t need intimate knowledge of the avr32 port structure to change the code without breaking it, and you don’t need intimate knowledge of the code to change the board layout without breaking it.
(and yes, the compiler is smart enough to inline the array values instead of actually looking them up.)
(and yes, you could use an enum instead of defines.)