#106

Yes - it is - just checked.

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#107

There are actually a few possible points where the PWR plane overlaps the gnd pads eg the switch beside it and the square pad of the GND header for the OLED - any of them could have issues I guess…

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#108

I think those other spots are ok. There is a keepout around the vias so they don’t connect to the power plane

#110

I’m being dumb - you’re right - that milling layer looks very suspect with the pwr layer - good spot !

Edit: Ok - it was that milling layer - filing out the hole cleared the short…

Definitely worth raising it as an issue on GitHub…

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#111

Awesome, thanks for verifying. I was planning to use JLCPCB to make my boards and assemble the passive components (which will save soldering several hundred 0402 size pads). I’ll fix that, cross my fingers, and give it a try!

P.s., If anyone else is interested: if all goes well I’ll have a few partially populated boards and panels to sell (I only want one for myself, but will be doing a run of 5 boards/panels).

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#112

@frankchannel well spotted. I

had to (and i think @forestcaver too) had to desolder each component one by one from the faulty board.

I tried drilling pretty much all around the 5v converter and eventually gave up. What puzzles me is there are working pcbs out there, i built two, so i guess someone spotted this error before :slight_smile:

I wish i could have known, would have saved me a good few hours of cursing and fustration!

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#113

Good spot, @frankchannel

#114

It could be that the engineers at the PCB fab house identified and fixed the error on boards that came out working. I believe @forestcaver said he sent the same set of gerbers to JLCPCB and PCBWAY (and the latter came out working). Either that, or the different PCB fabs interpret the same gerbers differently.

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#115

That’s my thinking too - different processes at the fabs…

#116

gerbers get exported differently according to your eagle DFM settings, which you configure prior to generating gerbers— sometimes with settings provided by your manufacturer ie oshpark.

so, yes, there may be some overlaps with the mill layer, but the DFM settings should create spacing so shorts don’t happen given minimum distances. this is one of the helpful things that eagle does, if you set it up right, and know how to use it.

secondarily, a good PCB manufacturer will have an engineer review your files prior to printing. most have automated software to spot common/likely mistakes.

#117

Good to know. I’m a bit of a novice, and appreciate the opportunity to learn, e.g., by investigating problems like this. I’m not sure where to change the DFM settings in Eagle. Is DFM the same as DRC? Because the tolerances setup in the DRC seem to be ignored in this case. I used the oshpark CAM files to generate gerbers, but the same thing happens with most of the other templates that are available.

#118

DRC, yes, apologies! was confusing my acronyms (design for manufacturing)

i’m confused why the settings would be ignored…

2 Likes
#119

Me too :). The hole milled for the USB jack goes right through the copper pour in the power plane. The DRC say there should be 10mil space there. I bumped that up to 30mil just to see, but nothing changed. It might be (?) because the holes in the USB jack “belong” to that specific part, so the interaction is ignored? Another example of this behaviour is the mounting holes for the standoffs. I tried to delete them and realized I couldn’t, until I discovered they are actually part of the OLED-screen part. I would have to edit the OLED-screen part in order to delete those holes. Maybe it has something to do with this hierarchical way of organizing things?

#120

Hi @forestcaver what did you do exactly to fix the issue?

#121

With a round file, I removed the plating in the northern part of the hole that corresponds to the overlap of the gnd and pwr internal planes.

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#122

I adjusted the copper pour in the power plane so that it does not intersect with any milling holes and placed an order with JLCPCB. Fingers crossed. If the boards come out ok, I’ll fork the repository and add my changes for others to use if they want.

If any Eagle experts can show me how to properly set the DRC settings and export the gerbers so that this problem doesn’t occur with the original .brd files I’d be really keen to see how it’s done.

3 Likes
#123

Curiously, the gerber’s I submitted to JLCPCB failed their internal audit due to the holes in the milling layer. The problem they have identified is with the slotted holes added to the thonkiconn jacks (which are shorted to the ground plane via the milling layer).

Edit: it seems slotted holes used on 4 layer boards can cause a lot of problems. See e.g., https://docs.oshpark.com/design-tools/eagle/cutouts-and-slots/

When using Slots with a 4 layer PCB, you MUST manually verify internal layers. Eagle’s DRC does not respect any method of making slots, and copper pours or auto-routed traces will short to the slot.

#124

15892923639772859419399777993348
158929236397728594193997779933483024×4032 2.48 MB

Patch not the forbidden param jack…

5 Likes
#125

Looks like you made your own boards (and added an extra input). Did you have any problems with the slotted holes in the milling layer (and if so, how did you deal with that)?

#126

Sorry, this was built at MSW so I don’t know what issues there were or weren’t with the fab.

The extra jack here was initially a panel design mistake but it is being repurposed as an I2C jack.

2 Likes