Here is the update that I promised. Wrote it yesterday - forgot to post it.
I’ve updated the Crazy Verbose Status + Timeline with the latest details. In short:
We’re still on track for my planned schedule of doing the final pricing, funds collecting and shipping at the beginning of next month (April).
Might slip a few days if life gets in the way - but I’ve got a good clip going right now.
I was able to get a lot of the little parts needed for assembly (jumpers, headers, etc.) cut to size and ready while I was recuperating from a cold and jet lag (and penguin joy). This will have me more ready for the assembly phase. Plus - I’ve moved like lightning through the TXi SMD work.
75% of the boards are complete; the only board left is the bottom board for the TXo. This is the most complex board, with a good number of components on both sides (including the pesky DAC). I’m moving pretty quickly now - but this one is going to take the remainder of the week and weekend to finish.
On @sam’s suggestion, I made a modification to my plans for the i2c cables. Originally I was making a black mark on one of the wires to help orient the ground wire. As they are multicolor, sometimes this worked and sometimes it was invisible. @sam tried using a sticker on his - which looked great:
The problem is - the pesky things would come loose on their own. I’m going to use a paint pen to clearly mark one of the sides so we don’t get confused (especially when one of the devices is racked).
TELEX HANDY LINKS
TELEX Microsite | Ordering Process Details | Crazy Verbose Status + Timeline
Open Source Repository | Printable Command Reference